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The tutorial demonstrates basic set-up and design methods available in the Open hardware xilinx 9.0 version of the ISE software. By the end of the tutorial, you will have a greater understanding of how to implement your own design flow using the ISE 9. Opej 9. After you have completed the tutorial, you will have an understanding of how to create, verify, and implement a design.

Note: This tutorial is designed for Xilinc 9. Accessing Help At any time open hardware xilinx 9.0 the tutorial, you can access online help for additional information about the ISE software and related tools. It contains information about creating and maintaining your complete design flow in ISE. To create a new project: 1. The New Project Wizard appears.

Type tutorial in the Project Name field. Enter or browse to a location directory path for the new project. A tutorial subdirectory is created automatically. Click Next to move to the device properties page. Leave the default values in the remaining fields. When the table is complete, your project properties will look like the following:.

At the end of the next section, your new project will be complete. Determine the language that you wish to use for the tutorial. Type in the file name counter. Verify that the Add to project checkbox is selected. Click Next. Declare the ports for the counter design by filling in the port information Open Hardware Xilinx 70 as shown below:. Click Next, then Next, then Finish. To do this you will use a simple counter code example from the ISE Language Templates and customize it for the counter design.

Place the cursor just below the begin statement within the counter architecture. This step copies the template into the counter source file. You have now created the VHDL open hardware xilinx 9.0 for the tutorial project.

Creating a Verilog Source Create the top-level Verilog source file for the project as follows: 1. Click New Source in the New Project dialog box. Select Open hardware xilinx 9.0 Module as the source type in the New Source dialog box.

Verify that the Add to Project checkbox open hardware xilinx 9.0 selected. Click Next, then Finish in the New Source Information dialog box to complete the new source file template.

The source file containing the counter module displays in the Workspace, and the counter displays in the Sources tab, as shown below:. Using Language Templates Verilog The next step in creating the new source is to add the behavioral description for open hardware xilinx 9.0. Use a simple counter code example from the ISE Language Hardwsre and customize it for the counter design.

Final Open hardware xilinx 9.0 of the Verilog Source 1. Checking the Open hardware xilinx 9.0 of the New Counter Module When the source files are complete, check the syntax of the design to find errors and typos.

Select the counter design source in the Sources window hhardware display the related processes in the Processes window. Double-click the Check Syntax process. Note: Hardwate must correct any errors found in your source files. You open hardware xilinx 9.0 check for errors in the Console tab of the Transcript window.

Xiilinx you continue without valid syntax, you will not be able to simulate or synthesize your design. Close the HDL file. Verifying Functionality using Behavioral Simulation Create a test bench waveform containing input stimulus you can use to verify the functionality of the counter module. The test bench waveform is a graphical view of a test bench.

Create the test bench waveform as follows: 1. Select the counter HDL file in open hardware xilinx 9.0 Sources window. The Associated Source page shows that you are associating the test bench waveform with the source file counter.

The Summary page shows that the source will be added to the project, and it displays the source directory, type and name. Click Finish. Open hardware xilinx 9.0 xlinx to set the clock frequency, setup time and output delay times in the Initialize Hardwarw open hardware xilinx 9.0 box before the test bench waveform editing window opens. The design requirements correspond with the values below.

Click Finish to complete the timing initialization. Save the waveform. In the Sources window, select the Behavioral Simulation view to see that the test bench waveform file is automatically added to your project. Simulating Design Functionality Verify that the counter design functions as you expect by performing behavior simulation as follows: 1.

The ISE Simulator opens and runs the simulation to the end of the test bench. To view your simulation results, select the Simulation tab and zoom in on the transitions. The simulation waveform results will look like the following:. Note: You can ignore any rows that start with TX. Verify that the counter is counting up and down as expected. Close the simulation view. Are you sure you want to close it? You have now completed simulation of your design using the ISE Simulator.

The timing is specified by entering constraints that guide the placement olen routing of the design. It is recommended that you enter global constraints. The clock period constraint specifies the clock frequency at which your design must operate inside the FPGA. Open hardware xilinx 9.0 Timing Constraints To constrain the design do the following: 1.

Select the counter HDL source file. You will be prompted with the following message:. Click Yes to add the hardqare file to your project.

The counter. The Xilinx Constraints Editor opens automatically. Click OK. Select the Pad to Setup toolbar button or double-click the empty Pad to Setup field to display the Pad to Setup dialog box. Select the Clock to Pad toolbar button or double-click the empty Clock to Pad field to display the Clock to Pad dialog box.

The constraints are displayed in the Constraints read-write tab, as shown below:. Save the timing constraints. Close the Constraints Editor. Implement Design and Verify Constraints Implement the design and verify that it meets the timing constraints specified in the previous section. Hardwqre the Design 1. Select the counter source file in the Sources window.

Double-click the Implement Design process in the Processes tab. Notice that after Implementation is complete, the Implementation processes have a green check mark next to them indicating that they completed successfully without Errors or Warnings.

Locate the Performance Summary table near the bottom of the Design Summary. Verify that the design meets the specified timing requirements. Assigning Pin Location Constraints Specify the pin locations for the ports of the design so that they are connected correctly on the Spartan-3 Startup Kit demo board. To constrain the design ports to package pins, do the following: 1. Verify that counter is selected in the Sources window.

Vivado Hardware Manager is open with a Digilent or Xilinx USB programming cable connected Board is power cycled or powered on If any configuration interface (except JTAG) is used and the JTAG cable is also connected, it is possible that the configuration will be interrupted by the JTAG chain auto detection and/or register reads and will not. When using SDK for the first time with a given workspace, select File > New > Project > Xilinx > Hardware Platform Specification to open the New Hardware Project dialog box. In this dialog box, you can specify the location of the hardware platform specification file. LogiCORE IP Aurora 64B/66B v www.- 4 PG October 2, Product Specification Introduction The Xilinx LogiCORE™ IP Aurora 64B/66B core is a scalable, lightweight, high data rate, link-layer protocol for high-speed serial communication. The protocol is open and can be implemented using Xilinx device technology.

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